(A) Field of the Invention
The present invention relates to a semiconductor memory and address-decoding circuit and method for decoding address, and more particularly, to a semiconductor memory and address-decoding circuit and method for decoding address by setting at least one bit of the address to disable a predetermined portion of the semiconductor memory.
(B) Description of the Related Art
The semiconductor memory is prepared by a series of fabrication processes such as lithographic process, etching process, and deposition process to form memory units and accessing circuits on the wafer, which is then sliced into several die and encapsulated after testing. However, it is unavoidable that some of the semiconductor memories prepared by the above fabrication process have defective memory cells without normal access function due to process variation.
Generally, semiconductor memory units with defective memory cells are pulled out during the testing process and discarded to prevent selling failed products on the market. To reduce the quantity of the discarded memory, the redundancy technique and the error correction code technique are used to allow semiconductor memory with small numbers of defective memory cells to operate normally. Consequently, the product yield can be increased.
In addition, semiconductor memory with different capacities, for example, 32 Mb or 64 Mb, are sold on the market for different applications. The manufacture of semiconductor memory requires different fabrication processes to manufacture different semiconductor memories of different capacities, which increases the fabrication cost.